1. Field of the Invention
The present invention relates to integrated circuits having latch circuitry that operates with asynchronous signals.
2. Description of the Prior Art
Latch circuits are widely used to capture and temporarily store logic signals in integrated circuits. For example referring to FIG. 6, a microprocessor (60) may receive inputs (I.sub.1, I.sub.2, I.sub.3) from a variety of external sources that are asynchronous from the microprocessor (60) clock (clock). A latch (65) at a given input (line 61) allows the external signal to be received at any time, and clocked out into the microprocessor circuitry at a time determined by the microprocessor clock. The design of a typical "DQ" latch is illustrated in FIG. 3. The clock signals SCK, MCKL and SCKL may be generated from the master clock signal MCK by the action of inverters 416, 417, 418, and 419 as shown in FIG. 4, with other clock schemes being possible.
The operation of the DQ circuit is as follows: A signal at the D input is passed through the transmission gates 300, 301 to node 302 when the "master" clock MCK is high (and SCK low). The inverters 303 and 304 supply the signal to node 305. The feedback transmission gates 306 and 307 provide positive feedback that holds the voltage at node 302 at its previous state (i.e., latches node 302) when signal SCKL is high (and MCKL low). The signal on node 305 is passed through transmission gates 308 and 309 when the "slave" clock signal SCK is high (and MCK low). The inverters 311 and 312 provide the output signal Q at node 313. The transmission gates 314 and 315 provide for latching node 313 when MCKL is high (and SCKL low) by conducting positive feedback to the input of inverter 311. The net result is that either a low or high logic level (e.g., V.sub.SS or V.sub.DD) at the D input is latched at the Q output when the clock MCK goes low. Thereafter, the Q output can not change state until the next high to low transition of the MCK clock.
One problem with latch circuitry occurs when the voltage at the D input changes at the same time that the clock signal MCK makes its high-to-low transition. For example, if the D input is making a low-to-high transition at that moment, then it is indeterminate whether a low or high voltage will appear at the Q output. In fact, the Q output may remain at an intermediate state midway between the logic levels (e.g., about V.sub.DD /2, which is 2.5 volts in the case of a 5 volt power supply) for an indefinite period of time. In that case, the output is said to be metastable, which is also referred to as being "hung". The time necessary to resolve the output, that is, to go to either a high or low stable state, is a measure of the effectiveness of the overall design of the latch circuitry.
To reduce the probability of a metastable output, circuit designers typically choose the gain of the inverters (303, 304, 311, and 312) to be relatively high. This provides a large positive feedback signal through the feedback transmission gates (306-307 and 314-315), in order to promote achieving a stable state in a short time period after the high-to-low transition of clock MCK. In addition, the clock signals to the feedback transmission gates (MCKL, SCKL) are typically delayed with respect to the clock signals MCK and SCK. This delay may be accomplished by inverters 417, 418, and 419 as shown in FIG. 4. The delayed clock signals MCKL and SCKL then help assure that the feedback signal applied to the input of inverter 303 arrives at the same time as the clock MCK is making a high-to-low transition (and SCK a low-to-high transition). In this manner, the possibility of contention between the D signal and the feedback signal is minimized. Such contention could otherwise pull node 302 in opposite directions, which would increase the probability that the output would hang. A similar situation obtains for the delayed clock signals applied to the feedback transmission gates 314 and 315.
Although these steps reduce the probability of a metastable output, it is still possible for a transition of the D input to occur so close in time to a transition of the MCK clock that a metastable output can occur. It can be seen that a metastable output can cause erroneous signals to be supplied to a microprocessor or other circuitry connected to the output of a latch. It is especially important that control signals not be erroneous, or else the instruction sequence may be altered. As a result, a large quantity of data may be corrupted by the erroneous signals. Therefore, still improved means for reducing the probability of a metastable latch output are desirable.